raddsp_fft_twiddle_rom Datasheet

Use Cases

Reusable FPGA DSP pipelines that need fixed-point, timing-aware implementation.

Block Diagram

VHDL Include And Instantiation Template

File Header

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library radhdl;
-- Direct entity instantiation below does not require importing the entity name.
use radhdl.dsp.all;
-- Narrower alternative: use radhdl.dsp_transform.all;

Component Declaration

component raddsp_fft_twiddle_rom is
  generic (
    VENDOR : string := "xilinx";
    DEVICE_FAMILY : string := "ultrascaleplus";
    G_POINTS : positive := 1024;
    G_TWIDDLE_WIDTH : positive := 16;
    G_INVERSE_FFT : boolean := false;
    G_MEMORY_STYLE : string := "block";
    G_INIT_FILE : string := "none"
  );
  port (
    clk : in std_logic;
    rst : in std_logic;
    addr_i : in std_logic_vector;
    twiddle_re_o : out signed(G_TWIDDLE_WIDTH - 1 downto 0);
    twiddle_im_o : out signed(G_TWIDDLE_WIDTH - 1 downto 0)
  );
end component;

Direct Entity Instantiation

u_raddsp_fft_twiddle_rom : entity radhdl.raddsp_fft_twiddle_rom
  generic map (
    VENDOR          => "xilinx",
    DEVICE_FAMILY   => "ultrascaleplus",
    G_POINTS        => 1024,
    G_TWIDDLE_WIDTH => 16,
    G_INVERSE_FFT   => false,
    G_MEMORY_STYLE  => "block",
    G_INIT_FILE     => "none"
  )
  port map (
    clk          => <clk_signal>,
    rst          => <rst_signal>,
    addr_i       => <addr_i_signal>,
    twiddle_re_o => <twiddle_re_o_signal>,
    twiddle_im_o => <twiddle_im_o_signal>
  );

Generics

Name	Type	Default	Description
VENDOR	string	"xilinx"	Selects the vendor-specific implementation path, usually XILINX for DSP48/XPM-backed builds or generic for portable RTL.
DEVICE_FAMILY	string	"ultrascaleplus"	Identifies the target FPGA family so wrappers can choose the correct primitive or conservative portable behavior.
G_POINTS	positive	1024	Sets the transform, frame, or vector size used by the datapath.
G_TWIDDLE_WIDTH	positive	16	Sets the bit width for G TWIDDLE WIDTH values carried by this module.
G_INVERSE_FFT	boolean	false	Sets the transform, frame, or vector size used by the datapath.
G_MEMORY_STYLE	string	"block"	Configures G MEMORY STYLE for this instance.
G_INIT_FILE	string	"none"	Configures G INIT FILE for this instance.

Ports

Name	Direction	Type	Description
clk	in	std_logic	Clock for the associated synchronous logic and handshake domain.
rst	in	std_logic	Active-high synchronous reset for this clock domain.
addr_i	in	std_logic_vector	Input addr i signal for this module.
twiddle_re_o	out	signed(G_TWIDDLE_WIDTH - 1 downto 0)	Output twiddle re o signal generated by this module.
twiddle_im_o	out	signed(G_TWIDDLE_WIDTH - 1 downto 0)	Output twiddle im o signal generated by this module.

Testbenches

No directly associated testbench was found.

Sources

dsp/hdl/raddsp/src/raddsp_fft_twiddle_rom.vhd