raddsp_axis_radfft_ddr Datasheet

Use Cases

AXI-Stream datapath integration where module boundaries need explicit ready/valid behavior.
Reusable FPGA DSP pipelines that need fixed-point, timing-aware implementation.
Memory-mapped control/status integration with software-visible register maps.

Block Diagram

VHDL Include And Instantiation Template

File Header

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library radhdl;
-- Direct entity instantiation below does not require importing the entity name.
use radhdl.dsp.all;
-- Narrower alternative: use radhdl.dsp_transform.all;

Component Declaration

component raddsp_axis_radfft_ddr is
  generic (
    VENDOR : string := "xilinx";
    DEVICE_FAMILY : string := "ultrascaleplus";
    G_AXI_ADDR_WIDTH : positive := 32;
    G_AXI_DATA_WIDTH : positive := 64;
    G_AXIS_DATA_WIDTH : positive := 64;
    G_AXI_LITE_ADDR_WIDTH : positive := 16;
    G_FIFO_DEPTH : positive := 1024;
    G_FIFO_FWFT : boolean := true;
    G_MAX_BURST_BEATS : positive := 64;
    G_FFT_POINTS : positive := 1024;
    G_FFT_RADIX : positive := 2;
    G_FFT_INPUT_WIDTH : positive := 32;
    G_FFT_TWIDDLE_WIDTH : positive := 16;
    G_FFT_OUTPUT_WIDTH : positive := 32;
    G_FFT_SCALE_EACH_STAGE : boolean := true;
    G_FFT_MEMORY_STYLE : string := "block";
    G_FFT_TWIDDLE_INIT_FILE : string := "../../mem/radfft_twiddle_1024_16_fft.mem";
    G_FFT_INVERSE : boolean := false;
    G_MAX_MULTIPLIER_LANES : positive := 16;
    G_XCORR_ENABLE : boolean := true;
    G_XCORR_FRAME_DEPTH : positive := 16384;
    G_XCORR_MEMORY_STYLE : string := "block";
    G_DEFAULT_REGION_BYTES : natural := 67108864
  );
  port (
    m_axis_tdata : out std_logic_vector(G_AXIS_DATA_WIDTH - 1 downto 0);
    m_axis_tvalid : out std_logic;
    m_axis_tready : in std_logic;
    m_axis_tlast : out std_logic;
    s_axis_tdata : in std_logic_vector(G_AXIS_DATA_WIDTH - 1 downto 0);
    s_axis_tvalid : in std_logic;
    s_axis_tready : out std_logic;
    s_axis_tlast : in std_logic;
    m_axi_awaddr : out std_logic_vector(G_AXI_ADDR_WIDTH - 1 downto 0);
    m_axi_awlen : out std_logic_vector(7 downto 0);
    m_axi_awsize : out std_logic_vector(2 downto 0);
    m_axi_awburst : out std_logic_vector(1 downto 0);
    m_axi_awvalid : out std_logic;
    m_axi_awready : in std_logic;
    m_axi_wdata : out std_logic_vector(G_AXI_DATA_WIDTH - 1 downto 0);
    m_axi_wstrb : out std_logic_vector((G_AXI_DATA_WIDTH / 8) - 1 downto 0);
    m_axi_wlast : out std_logic;
    m_axi_wvalid : out std_logic;
    m_axi_wready : in std_logic;
    m_axi_bresp : in std_logic_vector(1 downto 0);
    m_axi_bvalid : in std_logic;
    m_axi_bready : out std_logic;
    m_axi_araddr : out std_logic_vector(G_AXI_ADDR_WIDTH - 1 downto 0);
    m_axi_arlen : out std_logic_vector(7 downto 0);
    m_axi_arsize : out std_logic_vector(2 downto 0);
    m_axi_arburst : out std_logic_vector(1 downto 0);
    m_axi_arvalid : out std_logic;
    m_axi_arready : in std_logic;
    m_axi_rdata : in std_logic_vector(G_AXI_DATA_WIDTH - 1 downto 0);
    m_axi_rresp : in std_logic_vector(1 downto 0);
    m_axi_rlast : in std_logic;
    m_axi_rvalid : in std_logic;
    m_axi_rready : out std_logic;
    s_axi_awaddr : in std_logic_vector(G_AXI_LITE_ADDR_WIDTH - 1 downto 0);
    s_axi_awprot : in std_logic_vector(2 downto 0);
    s_axi_awvalid : in std_logic;
    s_axi_awready : out std_logic;
    s_axi_wdata : in std_logic_vector(31 downto 0);
    s_axi_wstrb : in std_logic_vector(3 downto 0);
    s_axi_wvalid : in std_logic;
    s_axi_wready : out std_logic;
    s_axi_bresp : out std_logic_vector(1 downto 0);
    s_axi_bvalid : out std_logic;
    s_axi_bready : in std_logic;
    s_axi_araddr : in std_logic_vector(G_AXI_LITE_ADDR_WIDTH - 1 downto 0);
    s_axi_arprot : in std_logic_vector(2 downto 0);
    s_axi_arvalid : in std_logic;
    s_axi_arready : out std_logic;
    s_axi_rdata : out std_logic_vector(31 downto 0);
    s_axi_rresp : out std_logic_vector(1 downto 0);
    s_axi_rvalid : out std_logic;
    s_axi_rready : in std_logic;
    clk : in std_logic;
    rstn : in std_logic;
    irq_o : out std_logic
  );
end component;

Direct Entity Instantiation

u_raddsp_axis_radfft_ddr : entity radhdl.raddsp_axis_radfft_ddr
  generic map (
    VENDOR                  => "xilinx",
    DEVICE_FAMILY           => "ultrascaleplus",
    G_AXI_ADDR_WIDTH        => 32,
    G_AXI_DATA_WIDTH        => 64,
    G_AXIS_DATA_WIDTH       => 64,
    G_AXI_LITE_ADDR_WIDTH   => 16,
    G_FIFO_DEPTH            => 1024,
    G_FIFO_FWFT             => true,
    G_MAX_BURST_BEATS       => 64,
    G_FFT_POINTS            => 1024,
    G_FFT_RADIX             => 2,
    G_FFT_INPUT_WIDTH       => 32,
    G_FFT_TWIDDLE_WIDTH     => 16,
    G_FFT_OUTPUT_WIDTH      => 32,
    G_FFT_SCALE_EACH_STAGE  => true,
    G_FFT_MEMORY_STYLE      => "block",
    G_FFT_TWIDDLE_INIT_FILE => "../../mem/radfft_twiddle_1024_16_fft.mem",
    G_FFT_INVERSE           => false,
    G_MAX_MULTIPLIER_LANES  => 16,
    G_XCORR_ENABLE          => true,
    G_XCORR_FRAME_DEPTH     => 16384,
    G_XCORR_MEMORY_STYLE    => "block",
    G_DEFAULT_REGION_BYTES  => 67108864
  )
  port map (
    m_axis_tdata  => <m_axis_tdata_signal>,
    m_axis_tvalid => <m_axis_tvalid_signal>,
    m_axis_tready => <m_axis_tready_signal>,
    m_axis_tlast  => <m_axis_tlast_signal>,
    s_axis_tdata  => <s_axis_tdata_signal>,
    s_axis_tvalid => <s_axis_tvalid_signal>,
    s_axis_tready => <s_axis_tready_signal>,
    s_axis_tlast  => <s_axis_tlast_signal>,
    m_axi_awaddr  => <m_axi_awaddr_signal>,
    m_axi_awlen   => <m_axi_awlen_signal>,
    m_axi_awsize  => <m_axi_awsize_signal>,
    m_axi_awburst => <m_axi_awburst_signal>,
    m_axi_awvalid => <m_axi_awvalid_signal>,
    m_axi_awready => <m_axi_awready_signal>,
    m_axi_wdata   => <m_axi_wdata_signal>,
    m_axi_wstrb   => <m_axi_wstrb_signal>,
    m_axi_wlast   => <m_axi_wlast_signal>,
    m_axi_wvalid  => <m_axi_wvalid_signal>,
    m_axi_wready  => <m_axi_wready_signal>,
    m_axi_bresp   => <m_axi_bresp_signal>,
    m_axi_bvalid  => <m_axi_bvalid_signal>,
    m_axi_bready  => <m_axi_bready_signal>,
    m_axi_araddr  => <m_axi_araddr_signal>,
    m_axi_arlen   => <m_axi_arlen_signal>,
    m_axi_arsize  => <m_axi_arsize_signal>,
    m_axi_arburst => <m_axi_arburst_signal>,
    m_axi_arvalid => <m_axi_arvalid_signal>,
    m_axi_arready => <m_axi_arready_signal>,
    m_axi_rdata   => <m_axi_rdata_signal>,
    m_axi_rresp   => <m_axi_rresp_signal>,
    m_axi_rlast   => <m_axi_rlast_signal>,
    m_axi_rvalid  => <m_axi_rvalid_signal>,
    m_axi_rready  => <m_axi_rready_signal>,
    s_axi_awaddr  => <s_axi_awaddr_signal>,
    s_axi_awprot  => <s_axi_awprot_signal>,
    s_axi_awvalid => <s_axi_awvalid_signal>,
    s_axi_awready => <s_axi_awready_signal>,
    s_axi_wdata   => <s_axi_wdata_signal>,
    s_axi_wstrb   => <s_axi_wstrb_signal>,
    s_axi_wvalid  => <s_axi_wvalid_signal>,
    s_axi_wready  => <s_axi_wready_signal>,
    s_axi_bresp   => <s_axi_bresp_signal>,
    s_axi_bvalid  => <s_axi_bvalid_signal>,
    s_axi_bready  => <s_axi_bready_signal>,
    s_axi_araddr  => <s_axi_araddr_signal>,
    s_axi_arprot  => <s_axi_arprot_signal>,
    s_axi_arvalid => <s_axi_arvalid_signal>,
    s_axi_arready => <s_axi_arready_signal>,
    s_axi_rdata   => <s_axi_rdata_signal>,
    s_axi_rresp   => <s_axi_rresp_signal>,
    s_axi_rvalid  => <s_axi_rvalid_signal>,
    s_axi_rready  => <s_axi_rready_signal>,
    clk           => <clk_signal>,
    rstn          => <rstn_signal>,
    irq_o         => <irq_o_signal>
  );

Generics

Name	Type	Default	Description
VENDOR	string	"xilinx"	Selects the vendor-specific implementation path, usually XILINX for DSP48/XPM-backed builds or generic for portable RTL.
DEVICE_FAMILY	string	"ultrascaleplus"	Identifies the target FPGA family so wrappers can choose the correct primitive or conservative portable behavior.
G_AXI_ADDR_WIDTH	positive	32	Sets the bit width for G AXI ADDR WIDTH values carried by this module.
G_AXI_DATA_WIDTH	positive	64	Sets the bit width for G AXI DATA WIDTH values carried by this module.
G_AXIS_DATA_WIDTH	positive	64	Sets the bit width for G AXIS DATA WIDTH values carried by this module.
G_AXI_LITE_ADDR_WIDTH	positive	16	Sets the bit width for G AXI LITE ADDR WIDTH values carried by this module.
G_FIFO_DEPTH	positive	1024	Sets the storage depth, frame length, or number of buffered samples used internally.
G_FIFO_FWFT	boolean	true	Configures G FIFO FWFT for this instance.
G_MAX_BURST_BEATS	positive	64	Configures G MAX BURST BEATS for this instance.
G_FFT_POINTS	positive	1024	Sets the transform, frame, or vector size used by the datapath.
G_FFT_RADIX	positive	2	Sets the transform, frame, or vector size used by the datapath.
G_FFT_INPUT_WIDTH	positive	32	Sets the bit width for G FFT INPUT WIDTH values carried by this module.
G_FFT_TWIDDLE_WIDTH	positive	16	Sets the bit width for G FFT TWIDDLE WIDTH values carried by this module.
G_FFT_OUTPUT_WIDTH	positive	32	Sets the bit width for G FFT OUTPUT WIDTH values carried by this module.
G_FFT_SCALE_EACH_STAGE	boolean	true	Sets the transform, frame, or vector size used by the datapath.
G_FFT_MEMORY_STYLE	string	"block"	Sets the transform, frame, or vector size used by the datapath.
G_FFT_TWIDDLE_INIT_FILE	string	"../../mem/radfft_twiddle_1024_16_fft.mem"	Sets the transform, frame, or vector size used by the datapath.
G_FFT_INVERSE	boolean	false	Sets the transform, frame, or vector size used by the datapath.
G_MAX_MULTIPLIER_LANES	positive	16	Sets the number of parallel sample lanes processed per handshake beat.
G_XCORR_ENABLE	boolean	true	Configures G XCORR ENABLE for this instance.
G_XCORR_FRAME_DEPTH	positive	16384	Sets the storage depth, frame length, or number of buffered samples used internally.
G_XCORR_MEMORY_STYLE	string	"block"	Configures G XCORR MEMORY STYLE for this instance.
G_DEFAULT_REGION_BYTES	natural	67108864	Configures G DEFAULT REGION BYTES for this instance.

Ports

Name	Direction	Type	Description
m_axis_tdata	out	std_logic_vector(G_AXIS_DATA_WIDTH - 1 downto 0)	Output AXI-stream payload containing packed processed result lanes.
m_axis_tvalid	out	std_logic	Output AXI-stream valid qualifier for the current result beat.
m_axis_tready	in	std_logic	Output AXI-stream ready input from the downstream block.
m_axis_tlast	out	std_logic	Output AXI-stream frame marker aligned with the processed result beat.
s_axis_tdata	in	std_logic_vector(G_AXIS_DATA_WIDTH - 1 downto 0)	Input AXI-stream payload containing packed sample or feature lanes.
s_axis_tvalid	in	std_logic	Input AXI-stream valid qualifier for the current sample beat.
s_axis_tready	out	std_logic	Input AXI-stream ready response indicating this block can accept a beat.
s_axis_tlast	in	std_logic	Input AXI-stream frame marker for the final beat of a frame.
m_axi_awaddr	out	std_logic_vector(G_AXI_ADDR_WIDTH - 1 downto 0)	AXI master-channel signal used for memory-mapped transfer generation.
m_axi_awlen	out	std_logic_vector(7 downto 0)	AXI master-channel signal used for memory-mapped transfer generation.
m_axi_awsize	out	std_logic_vector(2 downto 0)	AXI master-channel signal used for memory-mapped transfer generation.
m_axi_awburst	out	std_logic_vector(1 downto 0)	AXI master-channel signal used for memory-mapped transfer generation.
m_axi_awvalid	out	std_logic	AXI master-channel signal used for memory-mapped transfer generation.
m_axi_awready	in	std_logic	AXI master-channel signal used for memory-mapped transfer generation.
m_axi_wdata	out	std_logic_vector(G_AXI_DATA_WIDTH - 1 downto 0)	AXI master-channel signal used for memory-mapped transfer generation.
m_axi_wstrb	out	std_logic_vector((G_AXI_DATA_WIDTH / 8) - 1 downto 0)	AXI master-channel signal used for memory-mapped transfer generation.
m_axi_wlast	out	std_logic	AXI master-channel signal used for memory-mapped transfer generation.
m_axi_wvalid	out	std_logic	AXI master-channel signal used for memory-mapped transfer generation.
m_axi_wready	in	std_logic	AXI master-channel signal used for memory-mapped transfer generation.
m_axi_bresp	in	std_logic_vector(1 downto 0)	AXI master-channel signal used for memory-mapped transfer generation.
m_axi_bvalid	in	std_logic	AXI master-channel signal used for memory-mapped transfer generation.
m_axi_bready	out	std_logic	AXI master-channel signal used for memory-mapped transfer generation.
m_axi_araddr	out	std_logic_vector(G_AXI_ADDR_WIDTH - 1 downto 0)	AXI master-channel signal used for memory-mapped transfer generation.
m_axi_arlen	out	std_logic_vector(7 downto 0)	AXI master-channel signal used for memory-mapped transfer generation.
m_axi_arsize	out	std_logic_vector(2 downto 0)	AXI master-channel signal used for memory-mapped transfer generation.
m_axi_arburst	out	std_logic_vector(1 downto 0)	AXI master-channel signal used for memory-mapped transfer generation.
m_axi_arvalid	out	std_logic	AXI master-channel signal used for memory-mapped transfer generation.
m_axi_arready	in	std_logic	AXI master-channel signal used for memory-mapped transfer generation.
m_axi_rdata	in	std_logic_vector(G_AXI_DATA_WIDTH - 1 downto 0)	AXI master-channel signal used for memory-mapped transfer generation.
m_axi_rresp	in	std_logic_vector(1 downto 0)	AXI master-channel signal used for memory-mapped transfer generation.
m_axi_rlast	in	std_logic	AXI master-channel signal used for memory-mapped transfer generation.
m_axi_rvalid	in	std_logic	AXI master-channel signal used for memory-mapped transfer generation.
m_axi_rready	out	std_logic	AXI master-channel signal used for memory-mapped transfer generation.
s_axi_awaddr	in	std_logic_vector(G_AXI_LITE_ADDR_WIDTH - 1 downto 0)	AXI4-Lite slave-channel signal used for host register access.
s_axi_awprot	in	std_logic_vector(2 downto 0)	AXI4-Lite slave-channel signal used for host register access.
s_axi_awvalid	in	std_logic	AXI4-Lite slave-channel signal used for host register access.
s_axi_awready	out	std_logic	AXI4-Lite slave-channel signal used for host register access.
s_axi_wdata	in	std_logic_vector(31 downto 0)	AXI4-Lite slave-channel signal used for host register access.
s_axi_wstrb	in	std_logic_vector(3 downto 0)	AXI4-Lite slave-channel signal used for host register access.
s_axi_wvalid	in	std_logic	AXI4-Lite slave-channel signal used for host register access.
s_axi_wready	out	std_logic	AXI4-Lite slave-channel signal used for host register access.
s_axi_bresp	out	std_logic_vector(1 downto 0)	AXI4-Lite slave-channel signal used for host register access.
s_axi_bvalid	out	std_logic	AXI4-Lite slave-channel signal used for host register access.
s_axi_bready	in	std_logic	AXI4-Lite slave-channel signal used for host register access.
s_axi_araddr	in	std_logic_vector(G_AXI_LITE_ADDR_WIDTH - 1 downto 0)	AXI4-Lite slave-channel signal used for host register access.
s_axi_arprot	in	std_logic_vector(2 downto 0)	AXI4-Lite slave-channel signal used for host register access.
s_axi_arvalid	in	std_logic	AXI4-Lite slave-channel signal used for host register access.
s_axi_arready	out	std_logic	AXI4-Lite slave-channel signal used for host register access.
s_axi_rdata	out	std_logic_vector(31 downto 0)	AXI4-Lite slave-channel signal used for host register access.
s_axi_rresp	out	std_logic_vector(1 downto 0)	AXI4-Lite slave-channel signal used for host register access.
s_axi_rvalid	out	std_logic	AXI4-Lite slave-channel signal used for host register access.
s_axi_rready	in	std_logic	AXI4-Lite slave-channel signal used for host register access.
clk	in	std_logic	Clock for the associated synchronous logic and handshake domain.
rstn	in	std_logic	Active-low reset for this clock domain.
irq_o	out	std_logic	Output irq o signal generated by this module.

Register Interfaces

Static register maps are rendered below for this module.

Interface	Directions	Signals	Representative ports
M_AXI	in, out	25	m_axi_awaddr, m_axi_awlen, m_axi_awsize, m_axi_awburst, m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, +17 more
M_AXIS	in, out	4	m_axis_tdata, m_axis_tvalid, m_axis_tready, m_axis_tlast
S_AXI	in, out	19	s_axi_awaddr, s_axi_awprot, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready, +11 more
S_AXIS	in, out	4	s_axis_tdata, s_axis_tvalid, s_axis_tready, s_axis_tlast

Register Maps

raddsp_axis_radfft_ddr

Source: dsp/hdl/raddsp/register_maps/raddsp_axis_radfft_ddr.map.json

Software-visible control block for launching DDR-to-FFT, FFT-to-DDR, AXI-stream-to-DDR, and DDR-to-AXI-stream transfers.

Register	Offset	Access	Description
control	0x00	rw	Control register used to configure and control this block.
status	0x04	ro	bit 0: busy; bit 1: done; bit 2: error; bit 3: unsupported configuration
base_addr_lo	0x08	rw	Low 32 bits of the primary DDR source/base address.
base_addr_hi	0x0C	rw	High address bits of the primary DDR source/base address when the configured AXI address width exceeds 32 bits.
out_addr_lo	0x10	rw	Low 32 bits of the output DDR address. A zero value selects in-place output for supported operations.
out_addr_hi	0x14	rw	High address bits of the output DDR address when the configured AXI address width exceeds 32 bits.
length_bytes	0x18	rw	Transfer length in bytes. FFT operations require this to match the active frame size.
region_bytes	0x1C	rw	DDR region size used for range planning and default frame-region handling.
fft_points	0x20	rw	bits 7 downto 0: log2 FFT point count; bits 23 downto 16: AXI bytes per beat on readback
burst_beats	0x24	rw	bits 7 downto 0: requested AXI burst length in beats, clamped internally to the configured maximum
write_current	0x28	ro	Current low 32-bit AXI write address for active or recently completed stream-to-DDR activity.
read_current	0x2C	ro	Current low 32-bit AXI read address for active or recently completed DDR-to-stream or FFT input activity.
twiddle_addr_lo	0x30	rw	Low 32 bits of the DDR address containing FFT twiddle-table data.
twiddle_addr_hi	0x34	rw	High address bits of the FFT twiddle-table DDR address when the configured AXI address width exceeds 32 bits.
fft_config	0x38	rw	Control register used to configure and control this block.
magic	0x3C	ro	Read-only signature value 0x52464444 identifying the RadFFT DDR register block.
fft_limits	0x40	ro	bits 7 downto 0: maximum log2 FFT points; bits 15 downto 8: maximum input width; bits 23 downto 16: maximum output width; bits 31 downto 24: twiddle width
capabilities	0x44	ro	bit 0: radix-2 support; bit 1: radix-4 support; bit 2: DDR FFT support; bit 3: cross-correlation support; bits 15 downto 8: maximum multiplier lanes; bits 23 downto 16: AXI bytes per beat; bits 31 downto 24: maximum burst beats
batch_count	0x48	rw	Number of frames to process. A written value of zero is coerced to one.
src_stride_bytes	0x4C	rw	Byte stride between source frames for batched FFT operation. Zero selects the active frame size.
dst_stride_bytes	0x50	rw	Byte stride between destination frames for batched FFT operation. Zero selects the active frame size.
batch_done_count	0x54	ro	Number of frames completed in the current or most recent batched operation.
corr_b_addr_lo	0x58	rw	Low 32 bits of the secondary input address used by cross-correlation mode.
corr_b_addr_hi	0x5C	rw	High address bits of the secondary cross-correlation input address when the configured AXI address width exceeds 32 bits.
corr_scratch_addr_lo	0x60	rw	Low 32 bits of the scratch/output workspace address used during cross-correlation processing.
corr_scratch_addr_hi	0x64	rw	High address bits of the cross-correlation scratch workspace address when the configured AXI address width exceeds 32 bits.

control

Offset 0x00 / Access rw

Control register used to configure and control this block.

Control[15:0]

1514131211109876543210

RSVD [15:9]

IRQ EN

RSVD [7:6]

OPERATION MODE [5:4]

RSVD [3:1]

START CMD

Control[31:16]

31302928272625242322212019181716

CLEAR STICKY STAT FLAGS

RSVD [30:16]

Name	Register bit(s)	Description
CLEAR STICKY STAT FLAGS	Control[31]	Clears the associated sticky status flag(s).
IRQ EN	Control[8]	Enables interrupt generation for the associated event.
OPERATION MODE	Control[5:4]	Selects the operating mode.
START CMD	Control[0]	Starts the selected operation.

status

Offset 0x04 / Access ro

bit 0: busy; bit 1: done; bit 2: error; bit 3: unsupported configuration

Status[15:0]

1514131211109876543210

RSVD [15:4]

UNSUPPORTED CFG

ERROR

DONE

BUSY

Status[31:16]

31302928272625242322212019181716

RSVD [31:16]

Name	Register bit(s)	Description
UNSUPPORTED CFG	Status[3]	Unsupported configuration.
ERROR	Status[2]	Indicates that the block detected an error condition.
DONE	Status[1]	Indicates that the selected operation completed.
BUSY	Status[0]	Indicates that the block is actively processing.

base_addr_lo

Offset 0x08 / Access rw

Low 32 bits of the primary DDR source/base address.

BaseAddrLo[15:0]

1514131211109876543210

VALUE [15:0]

BaseAddrLo[31:16]

31302928272625242322212019181716

VALUE [31:16]

Name	Register bit(s)	Description
VALUE	BaseAddrLo[31:0]	Full register value.

base_addr_hi

Offset 0x0C / Access rw

High address bits of the primary DDR source/base address when the configured AXI address width exceeds 32 bits.

BaseAddrHi[15:0]

1514131211109876543210

VALUE [15:0]

BaseAddrHi[31:16]

31302928272625242322212019181716

VALUE [31:16]

Name	Register bit(s)	Description
VALUE	BaseAddrHi[31:0]	Full register value.

out_addr_lo

Offset 0x10 / Access rw

Low 32 bits of the output DDR address. A zero value selects in-place output for supported operations.

OutAddrLo[15:0]

1514131211109876543210

VALUE [15:0]

OutAddrLo[31:16]

31302928272625242322212019181716

VALUE [31:16]

Name	Register bit(s)	Description
VALUE	OutAddrLo[31:0]	Full register value.

out_addr_hi

Offset 0x14 / Access rw

High address bits of the output DDR address when the configured AXI address width exceeds 32 bits.

OutAddrHi[15:0]

1514131211109876543210

VALUE [15:0]

OutAddrHi[31:16]

31302928272625242322212019181716

VALUE [31:16]

Name	Register bit(s)	Description
VALUE	OutAddrHi[31:0]	Full register value.

length_bytes

Offset 0x18 / Access rw

Transfer length in bytes. FFT operations require this to match the active frame size.

LengthBytes[15:0]

1514131211109876543210

VALUE [15:0]

LengthBytes[31:16]

31302928272625242322212019181716

VALUE [31:16]

Name	Register bit(s)	Description
VALUE	LengthBytes[31:0]	Full register value.

region_bytes

Offset 0x1C / Access rw

DDR region size used for range planning and default frame-region handling.

RegionBytes[15:0]

1514131211109876543210

VALUE [15:0]

RegionBytes[31:16]

31302928272625242322212019181716

VALUE [31:16]

Name	Register bit(s)	Description
VALUE	RegionBytes[31:0]	Full register value.

fft_points

Offset 0x20 / Access rw

bits 7 downto 0: log2 FFT point count; bits 23 downto 16: AXI bytes per beat on readback

FftPoints[15:0]

1514131211109876543210

RSVD [15:8]

LOG2 FFT POINT COUNT [7:0]

FftPoints[31:16]

31302928272625242322212019181716

RSVD [31:24]

AXI BYTES PER BEAT ON READBACK [23:16]

Name	Register bit(s)	Description
AXI BYTES PER BEAT ON READBACK	FftPoints[23:16]	AXI bytes per beat on readback.
LOG2 FFT POINT COUNT	FftPoints[7:0]	Log2 FFT point count.

burst_beats

Offset 0x24 / Access rw

bits 7 downto 0: requested AXI burst length in beats, clamped internally to the configured maximum

BurstBeats[15:0]

1514131211109876543210

RSVD [15:8]

REQUESTED AXI BURST LENGTH IN BEATS [7:0]

BurstBeats[31:16]

31302928272625242322212019181716

RSVD [31:16]

Name	Register bit(s)	Description
REQUESTED AXI BURST LENGTH IN BEATS	BurstBeats[7:0]	Requested AXI burst length in beats.

write_current

Offset 0x28 / Access ro

Current low 32-bit AXI write address for active or recently completed stream-to-DDR activity.

WriteCurrent[15:0]

1514131211109876543210

VALUE [15:0]

WriteCurrent[31:16]

31302928272625242322212019181716

VALUE [31:16]

Name	Register bit(s)	Description
VALUE	WriteCurrent[31:0]	Full register value.

read_current

Offset 0x2C / Access ro

Current low 32-bit AXI read address for active or recently completed DDR-to-stream or FFT input activity.

ReadCurrent[15:0]

1514131211109876543210

VALUE [15:0]

ReadCurrent[31:16]

31302928272625242322212019181716

VALUE [31:16]

Name	Register bit(s)	Description
VALUE	ReadCurrent[31:0]	Full register value.

twiddle_addr_lo

Offset 0x30 / Access rw

Low 32 bits of the DDR address containing FFT twiddle-table data.

TwiddleAddrLo[15:0]

1514131211109876543210

VALUE [15:0]

TwiddleAddrLo[31:16]

31302928272625242322212019181716

VALUE [31:16]

Name	Register bit(s)	Description
VALUE	TwiddleAddrLo[31:0]	Full register value.

twiddle_addr_hi

Offset 0x34 / Access rw

High address bits of the FFT twiddle-table DDR address when the configured AXI address width exceeds 32 bits.

TwiddleAddrHi[15:0]

1514131211109876543210

VALUE [15:0]

TwiddleAddrHi[31:16]

31302928272625242322212019181716

VALUE [31:16]

Name	Register bit(s)	Description
VALUE	TwiddleAddrHi[31:0]	Full register value.

fft_config

Offset 0x38 / Access rw

Control register used to configure and control this block.

FftConfig[15:0]

1514131211109876543210

RSVD

OUTPUT WIDTH CODE [14:12]

RSVD

INPUT WIDTH CODE [10:8]

RSVD

CROSS CORRELATION MODE

RSVD PARALLEL MODE

RSVD RADIX MODE

RSVD [3:1]

RADIX 4 EN

FftConfig[31:16]

31302928272625242322212019181716

RSVD [31:18]

LANE COUNT CODE [17:16]

Name	Register bit(s)	Description
LANE COUNT CODE	FftConfig[17:16]	Lane count code.
OUTPUT WIDTH CODE	FftConfig[14:12]	Output width code.
INPUT WIDTH CODE	FftConfig[10:8]	Input width code.
CROSS CORRELATION MODE	FftConfig[6]	Selects the operating mode.
RSVD PARALLEL MODE	FftConfig[5]	Selects the operating mode.
RSVD RADIX MODE	FftConfig[4]	Selects the operating mode.
RADIX 4 EN	FftConfig[0]	Radix 4 enable.

magic

Offset 0x3C / Access ro

Read-only signature value 0x52464444 identifying the RadFFT DDR register block.

Magic[15:0]

1514131211109876543210

VALUE [15:0]

Magic[31:16]

31302928272625242322212019181716

VALUE [31:16]

Name	Register bit(s)	Description
VALUE	Magic[31:0]	Full register value.

fft_limits

Offset 0x40 / Access ro

bits 7 downto 0: maximum log2 FFT points; bits 15 downto 8: maximum input width; bits 23 downto 16: maximum output width; bits 31 downto 24: twiddle width

FftLimits[15:0]

1514131211109876543210

MAXIMUM INPUT WIDTH [15:8]

MAXIMUM LOG2 FFT POINTS [7:0]

FftLimits[31:16]

31302928272625242322212019181716

TWIDDLE WIDTH [31:24]

MAXIMUM OUTPUT WIDTH [23:16]

Name	Register bit(s)	Description
TWIDDLE WIDTH	FftLimits[31:24]	Twiddle width.
MAXIMUM OUTPUT WIDTH	FftLimits[23:16]	Maximum output width.
MAXIMUM INPUT WIDTH	FftLimits[15:8]	Maximum input width.
MAXIMUM LOG2 FFT POINTS	FftLimits[7:0]	Maximum log2 FFT points.

capabilities

Offset 0x44 / Access ro

bit 0: radix-2 support; bit 1: radix-4 support; bit 2: DDR FFT support; bit 3: cross-correlation support; bits 15 downto 8: maximum multiplier lanes; bits 23 downto 16: AXI bytes per beat; bits 31 downto 24: maximum burst beats

Capabilities[15:0]

1514131211109876543210

MAXIMUM MULTIPLIER LANES [15:8]

RSVD [7:4]

CROSS CORRELATION SUPPORT

DDR FFT SUPPORT

RADIX 4 SUPPORT

RADIX 2 SUPPORT

Capabilities[31:16]

31302928272625242322212019181716

MAXIMUM BURST BEATS [31:24]

AXI BYTES PER BEAT [23:16]

Name	Register bit(s)	Description
MAXIMUM BURST BEATS	Capabilities[31:24]	Maximum burst beats.
AXI BYTES PER BEAT	Capabilities[23:16]	AXI bytes per beat.
MAXIMUM MULTIPLIER LANES	Capabilities[15:8]	Maximum multiplier lanes.
CROSS CORRELATION SUPPORT	Capabilities[3]	Cross correlation support.
DDR FFT SUPPORT	Capabilities[2]	DDR FFT support.
RADIX 4 SUPPORT	Capabilities[1]	Radix 4 support.
RADIX 2 SUPPORT	Capabilities[0]	Radix 2 support.

batch_count

Offset 0x48 / Access rw

Number of frames to process. A written value of zero is coerced to one.

BatchCount[15:0]

1514131211109876543210

VALUE [15:0]

BatchCount[31:16]

31302928272625242322212019181716

VALUE [31:16]

Name	Register bit(s)	Description
VALUE	BatchCount[31:0]	Full register value.

src_stride_bytes

Offset 0x4C / Access rw

Byte stride between source frames for batched FFT operation. Zero selects the active frame size.

SrcStrideBytes[15:0]

1514131211109876543210

VALUE [15:0]

SrcStrideBytes[31:16]

31302928272625242322212019181716

VALUE [31:16]

Name	Register bit(s)	Description
VALUE	SrcStrideBytes[31:0]	Full register value.

dst_stride_bytes

Offset 0x50 / Access rw

Byte stride between destination frames for batched FFT operation. Zero selects the active frame size.

DstStrideBytes[15:0]

1514131211109876543210

VALUE [15:0]

DstStrideBytes[31:16]

31302928272625242322212019181716

VALUE [31:16]

Name	Register bit(s)	Description
VALUE	DstStrideBytes[31:0]	Full register value.

batch_done_count

Offset 0x54 / Access ro

Number of frames completed in the current or most recent batched operation.

BatchDoneCount[15:0]

1514131211109876543210

VALUE [15:0]

BatchDoneCount[31:16]

31302928272625242322212019181716

VALUE [31:16]

Name	Register bit(s)	Description
VALUE	BatchDoneCount[31:0]	Full register value.

corr_b_addr_lo

Offset 0x58 / Access rw

Low 32 bits of the secondary input address used by cross-correlation mode.

CorrBAddrLo[15:0]

1514131211109876543210

VALUE [15:0]

CorrBAddrLo[31:16]

31302928272625242322212019181716

VALUE [31:16]

Name	Register bit(s)	Description
VALUE	CorrBAddrLo[31:0]	Full register value.

corr_b_addr_hi

Offset 0x5C / Access rw

High address bits of the secondary cross-correlation input address when the configured AXI address width exceeds 32 bits.

CorrBAddrHi[15:0]

1514131211109876543210

VALUE [15:0]

CorrBAddrHi[31:16]

31302928272625242322212019181716

VALUE [31:16]

Name	Register bit(s)	Description
VALUE	CorrBAddrHi[31:0]	Full register value.

corr_scratch_addr_lo

Offset 0x60 / Access rw

Low 32 bits of the scratch/output workspace address used during cross-correlation processing.

CorrScratchAddrLo[15:0]

1514131211109876543210

VALUE [15:0]

CorrScratchAddrLo[31:16]

31302928272625242322212019181716

VALUE [31:16]

Name	Register bit(s)	Description
VALUE	CorrScratchAddrLo[31:0]	Full register value.

corr_scratch_addr_hi

Offset 0x64 / Access rw

High address bits of the cross-correlation scratch workspace address when the configured AXI address width exceeds 32 bits.

CorrScratchAddrHi[15:0]

1514131211109876543210

VALUE [15:0]

CorrScratchAddrHi[31:16]

31302928272625242322212019181716

VALUE [31:16]

Name	Register bit(s)	Description
VALUE	CorrScratchAddrHi[31:0]	Full register value.

Testbenches

tb_raddsp_axis_radfft_ddr interface timing diagram

Source: dsp/hdl/testbenches/tb_raddsp_axis_radfft_ddr.vhd

Self-checking or stimulus-focused testbench for axis radfft ddr. Exercises representative handshakes, reset behavior, frame boundaries, and numeric corner cases for regression runs.

Interface Timing Diagram

Source: dsp/hdl/testbenches/tb_raddsp_axis_radfft_ddr.vhd

Horizontal Vertical

clk

rstn

irq_o

M_AXI

M_AXIS

S_AXI

S_AXIS

M_AXI interface signals

M_AXI Interface Waveform

Source: dsp/hdl/testbenches/tb_raddsp_axis_radfft_ddr.vhd

Horizontal Vertical

m_axi_arburst

m_axi_awburst

m_axi_arready

m_axi_arvalid

m_axi_awready

m_axi_awvalid

m_axi_bready

m_axi_bvalid

m_axi_rlast

m_axi_rready

m_axi_rvalid

m_axi_wlast

m_axi_wready

m_axi_wvalid

m_axi_araddr

m_axi_arlen

m_axi_awaddr

m_axi_awlen

m_axi_rdata

m_axi_wdata

m_axi_arsize

m_axi_awsize

m_axi_bresp

m_axi_rresp

m_axi_wstrb

M_AXIS interface signals

M_AXIS Interface Waveform

Source: dsp/hdl/testbenches/tb_raddsp_axis_radfft_ddr.vhd

Horizontal Vertical

m_axis_tlast

m_axis_tready

m_axis_tvalid

m_axis_tdata

S_AXI interface signals

S_AXI Interface Waveform

Source: dsp/hdl/testbenches/tb_raddsp_axis_radfft_ddr.vhd

Horizontal Vertical

s_axi_arready

s_axi_arvalid

s_axi_awready

s_axi_awvalid

s_axi_bready

s_axi_bvalid

s_axi_rready

s_axi_rvalid

s_axi_wready

s_axi_wvalid

s_axi_araddr

s_axi_awaddr

s_axi_rdata

s_axi_wdata

s_axi_arprot

s_axi_awprot

s_axi_bresp

s_axi_rresp

s_axi_wstrb

S_AXIS interface signals

S_AXIS Interface Waveform

Source: dsp/hdl/testbenches/tb_raddsp_axis_radfft_ddr.vhd

Horizontal Vertical

s_axis_tlast

s_axis_tready

s_axis_tvalid

s_axis_tdata

tb_raddsp_axis_radfft_ddr_xcorr_1024 interface timing diagram

Source: dsp/hdl/testbenches/tb_raddsp_axis_radfft_ddr_xcorr_1024.vhd

Self-checking or stimulus-focused testbench for axis radfft ddr xcorr 1024. Exercises representative handshakes, reset behavior, frame boundaries, and numeric corner cases for regression runs.

Interface Timing Diagram

Source: dsp/hdl/testbenches/tb_raddsp_axis_radfft_ddr_xcorr_1024.vhd

Horizontal Vertical

clk

rstn

irq_o

M_AXI

M_AXIS

S_AXI

S_AXIS

M_AXI interface signals

M_AXI Interface Waveform

Source: dsp/hdl/testbenches/tb_raddsp_axis_radfft_ddr_xcorr_1024.vhd

Horizontal Vertical

m_axi_arburst

m_axi_awburst

m_axi_arready

m_axi_arvalid

m_axi_awready

m_axi_awvalid

m_axi_bready

m_axi_bvalid

m_axi_rlast

m_axi_rready

m_axi_rvalid

m_axi_wlast

m_axi_wready

m_axi_wvalid

m_axi_araddr

m_axi_arlen

m_axi_awaddr

m_axi_awlen

m_axi_rdata

m_axi_wdata

m_axi_arsize

m_axi_awsize

m_axi_bresp

m_axi_rresp

m_axi_wstrb

M_AXIS interface signals

M_AXIS Interface Waveform

Source: dsp/hdl/testbenches/tb_raddsp_axis_radfft_ddr_xcorr_1024.vhd

Horizontal Vertical

m_axis_tlast

m_axis_tready

m_axis_tvalid

m_axis_tdata

S_AXI interface signals

S_AXI Interface Waveform

Source: dsp/hdl/testbenches/tb_raddsp_axis_radfft_ddr_xcorr_1024.vhd

Horizontal Vertical

s_axi_arready

s_axi_arvalid

s_axi_awready

s_axi_awvalid

s_axi_bready

s_axi_bvalid

s_axi_rready

s_axi_rvalid

s_axi_wready

s_axi_wvalid

s_axi_araddr

s_axi_awaddr

s_axi_rdata

s_axi_wdata

s_axi_arprot

s_axi_awprot

s_axi_bresp

s_axi_rresp

s_axi_wstrb

S_AXIS interface signals

S_AXIS Interface Waveform

Source: dsp/hdl/testbenches/tb_raddsp_axis_radfft_ddr_xcorr_1024.vhd

Horizontal Vertical

s_axis_tlast

s_axis_tready

s_axis_tvalid

s_axis_tdata

Sources

dsp/hdl/raddsp/src/raddsp_axis_radfft_ddr.vhd