raddsp_axis_radfft_batch Datasheet

Use Cases

AXI-Stream datapath integration where module boundaries need explicit ready/valid behavior.
Reusable FPGA DSP pipelines that need fixed-point, timing-aware implementation.
Memory-mapped control/status integration with software-visible register maps.

Block Diagram

VHDL Include And Instantiation Template

File Header

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library radhdl;
-- Direct entity instantiation below does not require importing the entity name.
use radhdl.dsp.all;
-- Narrower alternative: use radhdl.dsp_transform.all;

Component Declaration

component raddsp_axis_radfft_batch is
  generic (
    VENDOR : string := "xilinx";
    DEVICE_FAMILY : string := "ultrascale+";
    G_POINTS : positive := 16;
    G_MAX_POINTS : positive := 2048;
    G_RADIX : positive := 2;
    G_INVERSE_FFT : boolean := false;
    G_INPUT_WIDTH : positive := 16;
    G_TWIDDLE_WIDTH : positive := 16;
    G_OUTPUT_WIDTH : positive := 32;
    G_SCALE_EACH_STAGE : boolean := true;
    G_MEMORY_STYLE : string := "block"
  );
  port (
    m_axis_tvalid : out std_logic;
    m_axis_tready : in std_logic;
    m_axis_tdata : out std_logic_vector((2 * G_OUTPUT_WIDTH) - 1 downto 0);
    m_axis_tlast : out std_logic;
    s_axis_tvalid : in std_logic;
    s_axis_tready : out std_logic;
    s_axis_tdata : in std_logic_vector((2 * G_INPUT_WIDTH) - 1 downto 0);
    s_axis_tlast : in std_logic;
    clk : in std_logic;
    rst : in std_logic;
    twiddle_addr_o : out std_logic_vector(31 downto 0);
    twiddle_re_i : in std_logic_vector(G_TWIDDLE_WIDTH - 1 downto 0);
    twiddle_im_i : in std_logic_vector(G_TWIDDLE_WIDTH - 1 downto 0);
    busy_o : out std_logic;
    frame_done_o : out std_logic
  );
end component;

Direct Entity Instantiation

u_raddsp_axis_radfft_batch : entity radhdl.raddsp_axis_radfft_batch
  generic map (
    VENDOR             => "xilinx",
    DEVICE_FAMILY      => "ultrascale+",
    G_POINTS           => 16,
    G_MAX_POINTS       => 2048,
    G_RADIX            => 2,
    G_INVERSE_FFT      => false,
    G_INPUT_WIDTH      => 16,
    G_TWIDDLE_WIDTH    => 16,
    G_OUTPUT_WIDTH     => 32,
    G_SCALE_EACH_STAGE => true,
    G_MEMORY_STYLE     => "block"
  )
  port map (
    m_axis_tvalid  => <m_axis_tvalid_signal>,
    m_axis_tready  => <m_axis_tready_signal>,
    m_axis_tdata   => <m_axis_tdata_signal>,
    m_axis_tlast   => <m_axis_tlast_signal>,
    s_axis_tvalid  => <s_axis_tvalid_signal>,
    s_axis_tready  => <s_axis_tready_signal>,
    s_axis_tdata   => <s_axis_tdata_signal>,
    s_axis_tlast   => <s_axis_tlast_signal>,
    clk            => <clk_signal>,
    rst            => <rst_signal>,
    twiddle_addr_o => <twiddle_addr_o_signal>,
    twiddle_re_i   => <twiddle_re_i_signal>,
    twiddle_im_i   => <twiddle_im_i_signal>,
    busy_o         => <busy_o_signal>,
    frame_done_o   => <frame_done_o_signal>
  );

Generics

Name	Type	Default	Description
VENDOR	string	"xilinx"	Selects the vendor-specific implementation path, usually XILINX for DSP48/XPM-backed builds or generic for portable RTL.
DEVICE_FAMILY	string	"ultrascale+"	Identifies the target FPGA family so wrappers can choose the correct primitive or conservative portable behavior.
G_POINTS	positive	16	Sets the transform, frame, or vector size used by the datapath.
G_MAX_POINTS	positive	2048	Sets the transform, frame, or vector size used by the datapath.
G_RADIX	positive	2	Configures G RADIX for this instance.
G_INVERSE_FFT	boolean	false	Sets the transform, frame, or vector size used by the datapath.
G_INPUT_WIDTH	positive	16	Sets the bit width for G INPUT WIDTH values carried by this module.
G_TWIDDLE_WIDTH	positive	16	Sets the bit width for G TWIDDLE WIDTH values carried by this module.
G_OUTPUT_WIDTH	positive	32	Sets the bit width for G OUTPUT WIDTH values carried by this module.
G_SCALE_EACH_STAGE	boolean	true	Configures G SCALE EACH STAGE for this instance.
G_MEMORY_STYLE	string	"block"	Configures G MEMORY STYLE for this instance.

Ports

Name	Direction	Type	Description
m_axis_tvalid	out	std_logic	Output AXI-stream valid qualifier for the current result beat.
m_axis_tready	in	std_logic	Output AXI-stream ready input from the downstream block.
m_axis_tdata	out	std_logic_vector((2 * G_OUTPUT_WIDTH) - 1 downto 0)	Output AXI-stream payload containing packed processed result lanes.
m_axis_tlast	out	std_logic	Output AXI-stream frame marker aligned with the processed result beat.
s_axis_tvalid	in	std_logic	Input AXI-stream valid qualifier for the current sample beat.
s_axis_tready	out	std_logic	Input AXI-stream ready response indicating this block can accept a beat.
s_axis_tdata	in	std_logic_vector((2 * G_INPUT_WIDTH) - 1 downto 0)	Input AXI-stream payload containing packed sample or feature lanes.
s_axis_tlast	in	std_logic	Input AXI-stream frame marker for the final beat of a frame.
clk	in	std_logic	Clock for the associated synchronous logic and handshake domain.
rst	in	std_logic	Active-high synchronous reset for this clock domain.
twiddle_addr_o	out	std_logic_vector(31 downto 0)	Output twiddle addr o signal generated by this module.
twiddle_re_i	in	std_logic_vector(G_TWIDDLE_WIDTH - 1 downto 0)	Input twiddle re i signal for this module.
twiddle_im_i	in	std_logic_vector(G_TWIDDLE_WIDTH - 1 downto 0)	Input twiddle im i signal for this module.
busy_o	out	std_logic	Output busy o signal generated by this module.
frame_done_o	out	std_logic	Output frame done o signal generated by this module.

Register Interfaces

No fixed register map was found; this section documents the exposed register/control interface ports.

Interface	Directions	Signals	Representative ports
M_AXIS	in, out	4	m_axis_tvalid, m_axis_tready, m_axis_tdata, m_axis_tlast
S_AXIS	in, out	4	s_axis_tvalid, s_axis_tready, s_axis_tdata, s_axis_tlast

Testbenches

No directly associated testbench was found.

Sources

dsp/hdl/raddsp/src/raddsp_axis_radfft_batch.vhd