raddsp_axis_radfft

File Header

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library radhdl;
-- Direct entity instantiation below does not require importing the entity name.
use radhdl.dsp.all;
-- Narrower alternative: use radhdl.dsp_transform.all;

Component Declaration

component raddsp_axis_radfft is
  generic (
    VENDOR : string := "xilinx";
    DEVICE_FAMILY : string := "ultrascale+";
    G_POINTS : positive := 16;
    G_MAX_POINTS : positive := 2048;
    G_RADIX : positive := 2;
    G_PIPELINED_STREAMING : boolean := false;
    G_INVERSE_FFT : boolean := false;
    G_INPUT_WIDTH : positive := 16;
    G_TWIDDLE_WIDTH : positive := 16;
    G_OUTPUT_WIDTH : positive := 32;
    G_SCALE_EACH_STAGE : boolean := true;
    G_MEMORY_STYLE : string := "block";
    G_TWIDDLE_MEMORY_STYLE : string := "block";
    G_TWIDDLE_INIT_FILE : string := "none";
    G_EXTERNAL_TWIDDLES : boolean := false;
    G_MULTIPLIER_LANES : positive := 1;
    G_MAX_MULTIPLIER_LANES : positive := 8;
    G_MEMORY_WORD_SAMPLES : positive := 1
  );
  port (
    m_axis_tvalid : out std_logic;
    m_axis_tready : in std_logic;
    m_axis_tdata : out std_logic_vector((2 * G_OUTPUT_WIDTH) - 1 downto 0);
    m_axis_tlast : out std_logic;
    s_axis_tvalid : in std_logic;
    s_axis_tready : out std_logic;
    s_axis_tdata : in std_logic_vector((2 * G_INPUT_WIDTH) - 1 downto 0);
    s_axis_tlast : in std_logic;
    clk : in std_logic;
    rst : in std_logic;
    runtime_inverse_i : in std_logic := '0';
    twiddle_addr_o : out std_logic_vector(31 downto 0);
    twiddle_re_i : in std_logic_vector(G_TWIDDLE_WIDTH - 1 downto 0);
    twiddle_im_i : in std_logic_vector(G_TWIDDLE_WIDTH - 1 downto 0);
    busy_o : out std_logic;
    frame_done_o : out std_logic
  );
end component;

Direct Entity Instantiation

u_raddsp_axis_radfft : entity radhdl.raddsp_axis_radfft
  generic map (
    VENDOR                 => "xilinx",
    DEVICE_FAMILY          => "ultrascale+",
    G_POINTS               => 16,
    G_MAX_POINTS           => 2048,
    G_RADIX                => 2,
    G_PIPELINED_STREAMING  => false,
    G_INVERSE_FFT          => false,
    G_INPUT_WIDTH          => 16,
    G_TWIDDLE_WIDTH        => 16,
    G_OUTPUT_WIDTH         => 32,
    G_SCALE_EACH_STAGE     => true,
    G_MEMORY_STYLE         => "block",
    G_TWIDDLE_MEMORY_STYLE => "block",
    G_TWIDDLE_INIT_FILE    => "none",
    G_EXTERNAL_TWIDDLES    => false,
    G_MULTIPLIER_LANES     => 1,
    G_MAX_MULTIPLIER_LANES => 8,
    G_MEMORY_WORD_SAMPLES  => 1
  )
  port map (
    m_axis_tvalid     => <m_axis_tvalid_signal>,
    m_axis_tready     => <m_axis_tready_signal>,
    m_axis_tdata      => <m_axis_tdata_signal>,
    m_axis_tlast      => <m_axis_tlast_signal>,
    s_axis_tvalid     => <s_axis_tvalid_signal>,
    s_axis_tready     => <s_axis_tready_signal>,
    s_axis_tdata      => <s_axis_tdata_signal>,
    s_axis_tlast      => <s_axis_tlast_signal>,
    clk               => <clk_signal>,
    rst               => <rst_signal>,
    runtime_inverse_i => <runtime_inverse_i_signal>,
    twiddle_addr_o    => <twiddle_addr_o_signal>,
    twiddle_re_i      => <twiddle_re_i_signal>,
    twiddle_im_i      => <twiddle_im_i_signal>,
    busy_o            => <busy_o_signal>,
    frame_done_o      => <frame_done_o_signal>
  );