raddsp_audio_stereo_balance_tdm

File Header

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library radhdl;
-- Direct entity instantiation below does not require importing the entity name.
use radhdl.dsp.all;
-- Narrower alternative: use radhdl.dsp_transform.all;

Component Declaration

component raddsp_audio_stereo_balance_tdm is
  generic (
    SAMPLE_WIDTH : positive := 24;
    COEFF_WIDTH : positive := 18;
    COEFF_FRAC_BITS : natural := 15
  );
  port (
    clk : in std_logic;
    rst : in std_logic;
    left_i : in std_logic_vector(SAMPLE_WIDTH - 1 downto 0);
    right_i : in std_logic_vector(SAMPLE_WIDTH - 1 downto 0);
    valid_i : in std_logic;
    pan_i : in std_logic_vector(7 downto 0);
    left_o : out std_logic_vector(SAMPLE_WIDTH - 1 downto 0);
    right_o : out std_logic_vector(SAMPLE_WIDTH - 1 downto 0);
    valid_o : out std_logic;
    busy_o : out std_logic
  );
end component;

Direct Entity Instantiation

u_raddsp_audio_stereo_balance_tdm : entity radhdl.raddsp_audio_stereo_balance_tdm
  generic map (
    SAMPLE_WIDTH    => 24,
    COEFF_WIDTH     => 18,
    COEFF_FRAC_BITS => 15
  )
  port map (
    clk     => <clk_signal>,
    rst     => <rst_signal>,
    left_i  => <left_i_signal>,
    right_i => <right_i_signal>,
    valid_i => <valid_i_signal>,
    pan_i   => <pan_i_signal>,
    left_o  => <left_o_signal>,
    right_o => <right_o_signal>,
    valid_o => <valid_o_signal>,
    busy_o  => <busy_o_signal>
  );