raddsp_audio_quad_lfo_wavetable

File Header

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library radhdl;
-- Direct entity instantiation below does not require importing the entity name.
use radhdl.dsp.all;
-- Narrower alternative: use radhdl.dsp_transform.all;

Component Declaration

component raddsp_audio_quad_lfo_wavetable is
  generic (
    SAMPLE_WIDTH : positive := 24;
    WAVE_WIDTH : positive := 16;
    PHASE_WIDTH : positive := 24;
    TABLE_ADDR_WIDTH : positive := 9;
    COEFF_WIDTH : positive := 18;
    COEFF_FRAC_BITS : natural := 15
  );
  port (
    clk : in std_logic;
    rst : in std_logic;
    sample_ce_i : in std_logic;
    phase_inc0_i : in std_logic_vector(PHASE_WIDTH - 1 downto 0);
    phase_inc1_i : in std_logic_vector(PHASE_WIDTH - 1 downto 0);
    phase_inc2_i : in std_logic_vector(PHASE_WIDTH - 1 downto 0);
    phase_inc3_i : in std_logic_vector(PHASE_WIDTH - 1 downto 0);
    wave_select_i : in std_logic_vector(7 downto 0);
    depth0_i : in std_logic_vector(COEFF_WIDTH - 1 downto 0);
    depth1_i : in std_logic_vector(COEFF_WIDTH - 1 downto 0);
    depth2_i : in std_logic_vector(COEFF_WIDTH - 1 downto 0);
    depth3_i : in std_logic_vector(COEFF_WIDTH - 1 downto 0);
    table_wr_en_i : in std_logic;
    table_wr_addr_i : in std_logic_vector(TABLE_ADDR_WIDTH + 1 downto 0);
    table_wr_data_i : in std_logic_vector(WAVE_WIDTH - 1 downto 0);
    lfo0_o : out std_logic_vector(SAMPLE_WIDTH - 1 downto 0);
    lfo1_o : out std_logic_vector(SAMPLE_WIDTH - 1 downto 0);
    lfo2_o : out std_logic_vector(SAMPLE_WIDTH - 1 downto 0);
    lfo3_o : out std_logic_vector(SAMPLE_WIDTH - 1 downto 0);
    valid_o : out std_logic;
    init_done_o : out std_logic;
    busy_o : out std_logic
  );
end component;

Direct Entity Instantiation

u_raddsp_audio_quad_lfo_wavetable : entity radhdl.raddsp_audio_quad_lfo_wavetable
  generic map (
    SAMPLE_WIDTH     => 24,
    WAVE_WIDTH       => 16,
    PHASE_WIDTH      => 24,
    TABLE_ADDR_WIDTH => 9,
    COEFF_WIDTH      => 18,
    COEFF_FRAC_BITS  => 15
  )
  port map (
    clk             => <clk_signal>,
    rst             => <rst_signal>,
    sample_ce_i     => <sample_ce_i_signal>,
    phase_inc0_i    => <phase_inc0_i_signal>,
    phase_inc1_i    => <phase_inc1_i_signal>,
    phase_inc2_i    => <phase_inc2_i_signal>,
    phase_inc3_i    => <phase_inc3_i_signal>,
    wave_select_i   => <wave_select_i_signal>,
    depth0_i        => <depth0_i_signal>,
    depth1_i        => <depth1_i_signal>,
    depth2_i        => <depth2_i_signal>,
    depth3_i        => <depth3_i_signal>,
    table_wr_en_i   => <table_wr_en_i_signal>,
    table_wr_addr_i => <table_wr_addr_i_signal>,
    table_wr_data_i => <table_wr_data_i_signal>,
    lfo0_o          => <lfo0_o_signal>,
    lfo1_o          => <lfo1_o_signal>,
    lfo2_o          => <lfo2_o_signal>,
    lfo3_o          => <lfo3_o_signal>,
    valid_o         => <valid_o_signal>,
    init_done_o     => <init_done_o_signal>,
    busy_o          => <busy_o_signal>
  );