raddsp_audio_poly_synth

File Header

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library radhdl;
-- Direct entity instantiation below does not require importing the entity name.
use radhdl.dsp.all;
-- Narrower alternative: use radhdl.dsp_transform.all;

Component Declaration

component raddsp_audio_poly_synth is
  generic (
    VOICE_COUNT : positive := 16;
    SAMPLE_WIDTH : positive := 24;
    WAVE_WIDTH : positive := 16;
    PHASE_WIDTH : positive := 24;
    TABLE_ADDR_WIDTH : positive := 8;
    COEFF_WIDTH : positive := 18;
    COEFF_FRAC_BITS : natural := 15;
    RESET_CONFIG_REGS : boolean := true
  );
  port (
    clk : in std_logic;
    rst : in std_logic;
    sample_ce_i : in std_logic;
    cfg_wr_en_i : in std_logic;
    cfg_addr_i : in std_logic_vector(7 downto 0);
    cfg_data_i : in std_logic_vector(31 downto 0);
    cfg_rd_en_i : in std_logic := '0';
    cfg_rd_addr_i : in std_logic_vector(7 downto 0) := (others => '0');
    cfg_data_o : out std_logic_vector(31 downto 0);
    cfg_rd_valid_o : out std_logic;
    cfg_error_o : out std_logic;
    table_wr_en_i : in std_logic;
    table_wr_addr_i : in std_logic_vector(TABLE_ADDR_WIDTH + 1 downto 0);
    table_wr_data_i : in std_logic_vector(WAVE_WIDTH - 1 downto 0);
    sample_o : out std_logic_vector(SAMPLE_WIDTH - 1 downto 0);
    valid_o : out std_logic;
    table_init_done_o : out std_logic;
    busy_o : out std_logic
  );
end component;

Direct Entity Instantiation

u_raddsp_audio_poly_synth : entity radhdl.raddsp_audio_poly_synth
  generic map (
    VOICE_COUNT       => 16,
    SAMPLE_WIDTH      => 24,
    WAVE_WIDTH        => 16,
    PHASE_WIDTH       => 24,
    TABLE_ADDR_WIDTH  => 8,
    COEFF_WIDTH       => 18,
    COEFF_FRAC_BITS   => 15,
    RESET_CONFIG_REGS => true
  )
  port map (
    clk               => <clk_signal>,
    rst               => <rst_signal>,
    sample_ce_i       => <sample_ce_i_signal>,
    cfg_wr_en_i       => <cfg_wr_en_i_signal>,
    cfg_addr_i        => <cfg_addr_i_signal>,
    cfg_data_i        => <cfg_data_i_signal>,
    cfg_rd_en_i       => <cfg_rd_en_i_signal>,
    cfg_rd_addr_i     => <cfg_rd_addr_i_signal>,
    cfg_data_o        => <cfg_data_o_signal>,
    cfg_rd_valid_o    => <cfg_rd_valid_o_signal>,
    cfg_error_o       => <cfg_error_o_signal>,
    table_wr_en_i     => <table_wr_en_i_signal>,
    table_wr_addr_i   => <table_wr_addr_i_signal>,
    table_wr_data_i   => <table_wr_data_i_signal>,
    sample_o          => <sample_o_signal>,
    valid_o           => <valid_o_signal>,
    table_init_done_o => <table_init_done_o_signal>,
    busy_o            => <busy_o_signal>
  );