raddsp_audio_dds_oscillator

File Header

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library radhdl;
-- Direct entity instantiation below does not require importing the entity name.
use radhdl.dsp.all;
-- Narrower alternative: use radhdl.dsp_transform.all;

Component Declaration

component raddsp_audio_dds_oscillator is
  generic (
    SAMPLE_WIDTH : positive := 24;
    WAVE_WIDTH : positive := 16;
    PHASE_WIDTH : positive := 24;
    COEFF_WIDTH : positive := 18;
    COEFF_FRAC_BITS : natural := 15
  );
  port (
    clk : in std_logic;
    rst : in std_logic;
    enable_i : in std_logic;
    phase_inc_i : in std_logic_vector(PHASE_WIDTH - 1 downto 0);
    wave_select_i : in std_logic_vector(1 downto 0);
    gain_i : in std_logic_vector(COEFF_WIDTH - 1 downto 0);
    sample_o : out std_logic_vector(SAMPLE_WIDTH - 1 downto 0);
    valid_o : out std_logic
  );
end component;

Direct Entity Instantiation

u_raddsp_audio_dds_oscillator : entity radhdl.raddsp_audio_dds_oscillator
  generic map (
    SAMPLE_WIDTH    => 24,
    WAVE_WIDTH      => 16,
    PHASE_WIDTH     => 24,
    COEFF_WIDTH     => 18,
    COEFF_FRAC_BITS => 15
  )
  port map (
    clk           => <clk_signal>,
    rst           => <rst_signal>,
    enable_i      => <enable_i_signal>,
    phase_inc_i   => <phase_inc_i_signal>,
    wave_select_i => <wave_select_i_signal>,
    gain_i        => <gain_i_signal>,
    sample_o      => <sample_o_signal>,
    valid_o       => <valid_o_signal>
  );