raddsp_axis_matrix_elementwise Datasheet

Use Cases

AXI-Stream datapath integration where module boundaries need explicit ready/valid behavior.
Reusable FPGA DSP pipelines that need fixed-point, timing-aware implementation.
Memory-mapped control/status integration with software-visible register maps.

Block Diagram

VHDL Include And Instantiation Template

File Header

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library radhdl;
-- Direct entity instantiation below does not require importing the entity name.
use radhdl.dsp.all;
-- Narrower alternative: use radhdl.dsp_matrix.all;

Component Declaration

component raddsp_axis_matrix_elementwise is
  generic (
    VENDOR : string := "xilinx";
    DEVICE_FAMILY : string := "generic";
    DATA_WIDTH : positive := 16;
    COEFF_FRAC_BITS : natural := 15
  );
  port (
    s0_axis_tvalid : in std_logic;
    s0_axis_tready : out std_logic;
    s0_axis_tdata : in std_logic_vector(DATA_WIDTH - 1 downto 0);
    s0_axis_tlast : in std_logic;
    s1_axis_tvalid : in std_logic;
    s1_axis_tready : out std_logic;
    s1_axis_tdata : in std_logic_vector(DATA_WIDTH - 1 downto 0);
    s1_axis_tlast : in std_logic;
    m_axis_tvalid : out std_logic;
    m_axis_tready : in std_logic;
    m_axis_tdata : out std_logic_vector(DATA_WIDTH - 1 downto 0);
    m_axis_tlast : out std_logic;
    clk : in std_logic;
    rst : in std_logic;
    op_i : in std_logic_vector(1 downto 0)
  );
end component;

Direct Entity Instantiation

u_raddsp_axis_matrix_elementwise : entity radhdl.raddsp_axis_matrix_elementwise
  generic map (
    VENDOR          => "xilinx",
    DEVICE_FAMILY   => "generic",
    DATA_WIDTH      => 16,
    COEFF_FRAC_BITS => 15
  )
  port map (
    s0_axis_tvalid => <s0_axis_tvalid_signal>,
    s0_axis_tready => <s0_axis_tready_signal>,
    s0_axis_tdata  => <s0_axis_tdata_signal>,
    s0_axis_tlast  => <s0_axis_tlast_signal>,
    s1_axis_tvalid => <s1_axis_tvalid_signal>,
    s1_axis_tready => <s1_axis_tready_signal>,
    s1_axis_tdata  => <s1_axis_tdata_signal>,
    s1_axis_tlast  => <s1_axis_tlast_signal>,
    m_axis_tvalid  => <m_axis_tvalid_signal>,
    m_axis_tready  => <m_axis_tready_signal>,
    m_axis_tdata   => <m_axis_tdata_signal>,
    m_axis_tlast   => <m_axis_tlast_signal>,
    clk            => <clk_signal>,
    rst            => <rst_signal>,
    op_i           => <op_i_signal>
  );

Generics

Name	Type	Default	Description
VENDOR	string	"xilinx"	Selects the vendor-specific implementation path, usually XILINX for DSP48/XPM-backed builds or generic for portable RTL.
DEVICE_FAMILY	string	"generic"	Identifies the target FPGA family so wrappers can choose the correct primitive or conservative portable behavior.
DATA_WIDTH	positive	16	Sets the bit width for DATA WIDTH values carried by this module.
COEFF_FRAC_BITS	natural	15	Sets coefficient precision or coefficient count for the fixed-point DSP operation.

Ports

Name	Direction	Type	Description
s0_axis_tvalid	in	std_logic	S0 axis tvalid interface signal.
s0_axis_tready	out	std_logic	S0 axis tready interface signal.
s0_axis_tdata	in	std_logic_vector(DATA_WIDTH - 1 downto 0)	S0 axis tdata interface signal.
s0_axis_tlast	in	std_logic	S0 axis tlast interface signal.
s1_axis_tvalid	in	std_logic	S1 axis tvalid interface signal.
s1_axis_tready	out	std_logic	S1 axis tready interface signal.
s1_axis_tdata	in	std_logic_vector(DATA_WIDTH - 1 downto 0)	S1 axis tdata interface signal.
s1_axis_tlast	in	std_logic	S1 axis tlast interface signal.
m_axis_tvalid	out	std_logic	Output AXI-stream valid qualifier for the current result beat.
m_axis_tready	in	std_logic	Output AXI-stream ready input from the downstream block.
m_axis_tdata	out	std_logic_vector(DATA_WIDTH - 1 downto 0)	Output AXI-stream payload containing packed processed result lanes.
m_axis_tlast	out	std_logic	Output AXI-stream frame marker aligned with the processed result beat.
clk	in	std_logic	Clock for the associated synchronous logic and handshake domain.
rst	in	std_logic	Active-high synchronous reset for this clock domain.
op_i	in	std_logic_vector(1 downto 0)	Input op i signal for this module.

Register Interfaces

No fixed register map was found; this section documents the exposed register/control interface ports.

Interface	Directions	Signals	Representative ports
M_AXIS	in, out	4	m_axis_tvalid, m_axis_tready, m_axis_tdata, m_axis_tlast

Testbenches

tb_raddsp_axis_smoke reference plots

Source: dsp/hdl/testbenches/tb_raddsp_axis_smoke.vhd

Self-checking or stimulus-focused testbench for axis smoke. Exercises representative handshakes, reset behavior, frame boundaries, and numeric corner cases for regression runs.

Interface Timing Diagram

Source: dsp/hdl/testbenches/tb_raddsp_axis_smoke.vhd

Horizontal Vertical

clk

rst

s0_axis_tlast

s0_axis_tready

s0_axis_tvalid

s1_axis_tlast

s1_axis_tready

s1_axis_tvalid

s0_axis_tdata

s1_axis_tdata

op_i

M_AXIS

M_AXIS interface signals

M_AXIS Interface Waveform

Source: dsp/hdl/testbenches/tb_raddsp_axis_smoke.vhd

Horizontal Vertical

m_axis_tlast

m_axis_tready

m_axis_tvalid

m_axis_tdata

Sources

dsp/hdl/raddsp/src/raddsp_axis_matrix_elementwise.vhd