zc_chirp_frame_detector Datasheet

Use Cases

Reusable RadHDL building block for graph-generated FPGA systems.

Block Diagram

VHDL Include And Instantiation Template

File Header

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library radhdl;
-- Direct entity instantiation below does not require importing the entity name.
use radhdl.dsp.all;
-- Narrower alternative: use radhdl.dsp_detection.all;

Component Declaration

component zc_chirp_frame_detector is
  generic (
    DEVICE_FAMILY : string := "7series";
    G_SAMPLE_WIDTH : integer := 16;
    G_ACC_WIDTH : integer := 40;
    G_FRAME_SAMPLES : integer := 1024;
    G_CHIRP_LEN : integer := 512;
    G_CHIRP_AFTER_PEAK : integer := 160;
    G_PRODUCT_SHIFT : integer := 15
  );
  port (
    clk : in std_logic;
    rst : in std_logic;
    frame_start : in std_logic;
    sample_valid : in std_logic;
    sample_i : in signed(G_SAMPLE_WIDTH - 1 downto 0);
    sample_q : in signed(G_SAMPLE_WIDTH - 1 downto 0);
    sample_ready : out std_logic;
    processing : out std_logic;
    peak_valid : out std_logic;
    peak_index : out integer range 0 to G_FRAME_SAMPLES - 1;
    peak_i : out signed(G_ACC_WIDTH - 1 downto 0);
    peak_q : out signed(G_ACC_WIDTH - 1 downto 0);
    chirp_valid : out std_logic;
    chirp_index : out integer range 0 to G_CHIRP_LEN - 1;
    chirp_i : out signed(G_SAMPLE_WIDTH - 1 downto 0);
    chirp_q : out signed(G_SAMPLE_WIDTH - 1 downto 0);
    chirp_done : out std_logic
  );
end component;

Direct Entity Instantiation

u_zc_chirp_frame_detector : entity radhdl.zc_chirp_frame_detector
  generic map (
    DEVICE_FAMILY      => "7series",
    G_SAMPLE_WIDTH     => 16,
    G_ACC_WIDTH        => 40,
    G_FRAME_SAMPLES    => 1024,
    G_CHIRP_LEN        => 512,
    G_CHIRP_AFTER_PEAK => 160,
    G_PRODUCT_SHIFT    => 15
  )
  port map (
    clk          => <clk_signal>,
    rst          => <rst_signal>,
    frame_start  => <frame_start_signal>,
    sample_valid => <sample_valid_signal>,
    sample_i     => <sample_i_signal>,
    sample_q     => <sample_q_signal>,
    sample_ready => <sample_ready_signal>,
    processing   => <processing_signal>,
    peak_valid   => <peak_valid_signal>,
    peak_index   => <peak_index_signal>,
    peak_i       => <peak_i_signal>,
    peak_q       => <peak_q_signal>,
    chirp_valid  => <chirp_valid_signal>,
    chirp_index  => <chirp_index_signal>,
    chirp_i      => <chirp_i_signal>,
    chirp_q      => <chirp_q_signal>,
    chirp_done   => <chirp_done_signal>
  );

Generics

Name	Type	Default	Description
DEVICE_FAMILY	string	"7series"	Identifies the target FPGA family so wrappers can choose the correct primitive or conservative portable behavior.
G_SAMPLE_WIDTH	integer	16	Sets the bit width for G SAMPLE WIDTH values carried by this module.
G_ACC_WIDTH	integer	40	Sets the bit width for G ACC WIDTH values carried by this module.
G_FRAME_SAMPLES	integer	1024	Sets the width or count of samples handled by the datapath.
G_CHIRP_LEN	integer	512	Configures G CHIRP LEN for this instance.
G_CHIRP_AFTER_PEAK	integer	160	Configures G CHIRP AFTER PEAK for this instance.
G_PRODUCT_SHIFT	integer	15	Identifies the target FPGA family so wrappers can choose the correct primitive or conservative portable behavior.

Ports

Name	Direction	Type	Description
clk	in	std_logic	Clock for the associated synchronous logic and handshake domain.
rst	in	std_logic	Active-high synchronous reset for this clock domain.
frame_start	in	std_logic	Frame start interface signal.
sample_valid	in	std_logic	Sample valid interface signal.
sample_i	in	signed(G_SAMPLE_WIDTH - 1 downto 0)	Input sample vector captured or processed by the datapath.
sample_q	in	signed(G_SAMPLE_WIDTH - 1 downto 0)	Sample q interface signal.
sample_ready	out	std_logic	Sample ready interface signal.
processing	out	std_logic	Processing interface signal.
peak_valid	out	std_logic	Peak valid interface signal.
peak_index	out	integer range 0 to G_FRAME_SAMPLES - 1	Peak index interface signal.
peak_i	out	signed(G_ACC_WIDTH - 1 downto 0)	Input peak i signal for this module.
peak_q	out	signed(G_ACC_WIDTH - 1 downto 0)	Peak q interface signal.
chirp_valid	out	std_logic	Chirp valid interface signal.
chirp_index	out	integer range 0 to G_CHIRP_LEN - 1	Chirp index interface signal.
chirp_i	out	signed(G_SAMPLE_WIDTH - 1 downto 0)	Input chirp i signal for this module.
chirp_q	out	signed(G_SAMPLE_WIDTH - 1 downto 0)	Chirp q interface signal.
chirp_done	out	std_logic	Chirp done interface signal.

Testbenches

tb_zc_chirp_frame_detector_iqcal interface timing diagram

Source: dsp/hdl/testbenches/tb_zc_chirp_frame_detector_iqcal.vhd

Self-checking or stimulus-focused testbench for zc chirp frame detector iqcal. Exercises representative handshakes, reset behavior, frame boundaries, and numeric corner cases for regression runs.

Interface Timing Diagram

Source: dsp/hdl/testbenches/tb_zc_chirp_frame_detector_iqcal.vhd

Horizontal Vertical

clk

rst

chirp_done

chirp_valid

frame_start

peak_valid

sample_ready

sample_valid

chirp_i

chirp_index

chirp_q

peak_i

peak_index

peak_q

processing

sample_i

sample_q

Sources

dsp/hdl/raddsp/src/zc_chirp_frame_detector.vhd