raddsp_axis_fingerprint_matcher

File Header

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library radhdl;
-- Direct entity instantiation below does not require importing the entity name.
use radhdl.dsp.all;
-- Narrower alternative: use radhdl.dsp_detection.all;

Component Declaration

component raddsp_axis_fingerprint_matcher is
  generic (
    VENDOR : string := "xilinx";
    DEVICE_FAMILY : string := "generic";
    HASH_WIDTH : positive := 64;
    META_WIDTH : positive := 32;
    TABLE_ADDR_WIDTH : positive := 10;
    AXI_ADDR_WIDTH : positive := 8;
    AXI_DATA_WIDTH : positive := 32;
    MEMORY_STYLE : string := "block"
  );
  port (
    m_axis_tvalid : out std_logic;
    m_axis_tready : in std_logic;
    m_axis_tdata : out std_logic_vector(HASH_WIDTH + META_WIDTH + 32 - 1 downto 0);
    m_axis_tlast : out std_logic;
    s_axis_tvalid : in std_logic;
    s_axis_tready : out std_logic;
    s_axis_tdata : in std_logic_vector(HASH_WIDTH + 64 - 1 downto 0);
    s_axis_tlast : in std_logic;
    s_axi_awaddr : in std_logic_vector(AXI_ADDR_WIDTH - 1 downto 0);
    s_axi_awprot : in std_logic_vector(2 downto 0);
    s_axi_awvalid : in std_logic;
    s_axi_awready : out std_logic;
    s_axi_wdata : in std_logic_vector(AXI_DATA_WIDTH - 1 downto 0);
    s_axi_wstrb : in std_logic_vector((AXI_DATA_WIDTH / 8) - 1 downto 0);
    s_axi_wvalid : in std_logic;
    s_axi_wready : out std_logic;
    s_axi_bresp : out std_logic_vector(1 downto 0);
    s_axi_bvalid : out std_logic;
    s_axi_bready : in std_logic;
    s_axi_araddr : in std_logic_vector(AXI_ADDR_WIDTH - 1 downto 0);
    s_axi_arprot : in std_logic_vector(2 downto 0);
    s_axi_arvalid : in std_logic;
    s_axi_arready : out std_logic;
    s_axi_rdata : out std_logic_vector(AXI_DATA_WIDTH - 1 downto 0);
    s_axi_rresp : out std_logic_vector(1 downto 0);
    s_axi_rvalid : out std_logic;
    s_axi_rready : in std_logic;
    clk : in std_logic;
    rst : in std_logic;
    match_irq_o : out std_logic
  );
end component;

Direct Entity Instantiation

u_raddsp_axis_fingerprint_matcher : entity radhdl.raddsp_axis_fingerprint_matcher
  generic map (
    VENDOR           => "xilinx",
    DEVICE_FAMILY    => "generic",
    HASH_WIDTH       => 64,
    META_WIDTH       => 32,
    TABLE_ADDR_WIDTH => 10,
    AXI_ADDR_WIDTH   => 8,
    AXI_DATA_WIDTH   => 32,
    MEMORY_STYLE     => "block"
  )
  port map (
    m_axis_tvalid => <m_axis_tvalid_signal>,
    m_axis_tready => <m_axis_tready_signal>,
    m_axis_tdata  => <m_axis_tdata_signal>,
    m_axis_tlast  => <m_axis_tlast_signal>,
    s_axis_tvalid => <s_axis_tvalid_signal>,
    s_axis_tready => <s_axis_tready_signal>,
    s_axis_tdata  => <s_axis_tdata_signal>,
    s_axis_tlast  => <s_axis_tlast_signal>,
    s_axi_awaddr  => <s_axi_awaddr_signal>,
    s_axi_awprot  => <s_axi_awprot_signal>,
    s_axi_awvalid => <s_axi_awvalid_signal>,
    s_axi_awready => <s_axi_awready_signal>,
    s_axi_wdata   => <s_axi_wdata_signal>,
    s_axi_wstrb   => <s_axi_wstrb_signal>,
    s_axi_wvalid  => <s_axi_wvalid_signal>,
    s_axi_wready  => <s_axi_wready_signal>,
    s_axi_bresp   => <s_axi_bresp_signal>,
    s_axi_bvalid  => <s_axi_bvalid_signal>,
    s_axi_bready  => <s_axi_bready_signal>,
    s_axi_araddr  => <s_axi_araddr_signal>,
    s_axi_arprot  => <s_axi_arprot_signal>,
    s_axi_arvalid => <s_axi_arvalid_signal>,
    s_axi_arready => <s_axi_arready_signal>,
    s_axi_rdata   => <s_axi_rdata_signal>,
    s_axi_rresp   => <s_axi_rresp_signal>,
    s_axi_rvalid  => <s_axi_rvalid_signal>,
    s_axi_rready  => <s_axi_rready_signal>,
    clk           => <clk_signal>,
    rst           => <rst_signal>,
    match_irq_o   => <match_irq_o_signal>
  );